1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. More particularly, the present invention relates to a metal oxide semiconductor device of nanometer scale and a fabrication method thereof.
2. Description of Related Art
As the level of integration of integrated devices increases, the dimensions of integrated devices decrease correspondingly. Accordingly, as the dimension of a metal oxide semiconductor (MOS) device is being reduced, the channel length also reduces. However, the dimension of the channel of a MOS transistor can not be unlimitedly reduced. As the channel length reduces to a certain degree, various problems gradually surface. The so-called short channel effect not only lowers the device threshold voltage (Vt) and creates the controlling problem of the MOS transistor by the gate voltage (Vg), the operation of the MOS transistor is also affected by the punch-through effect. Especially when the transistor dimension of a metal oxide semiconductor (MOS) device is further reduced to the nanometer scale, the short channel effect and the punch through effect would become more serious and a further size reduction of the semiconductor device is hindered.
Many studies have been done on approaches to suppress the short channel effect and the punch through effect. FIG. 1 is a cross-sectional view of a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device is constructed with a substrate 100, a gate structure 102, a spacer 108, a source region 110 and a drain region 112, a lightly doped region 114 and a pocket implant region 116. The gate structure 102 is disposed above the substrate 100, and the gate structure 102 is constituted with a gate oxide layer 104 and a gate conductive layer 106. A spacer 108 is disposed on the sidewall of the gate structure 102. The source region 110 and the drain region are configured in the substrate 100 beside both sides of the gate structure 102. The light doped regions 114 are configured in the substrate 100 below the spacer 108, contiguous to the source region 110 and the drain region. The pocket implant region 116, also known as a halo implant region, is disposed under the light doped region 114. The dopant type of the pocket doped region 116 is different from the dopant type of the lightly doped region 114 and the source 110/drain 112 region in order to suppress the short channel effect and the punch through effect of the semiconductor device.
In the above semiconductor device, forming a doped region (pocket implant region) with a different dopant type from that of the light doped region under the light doped region 114 can suppress the short channel effect and the punch through effect of the semiconductor device. However, during the fabrication of such a semiconductor device, several thermal processes need to be conducted. As a result, the diffusion of the dopants in the pocket implant region occurs. The effectiveness on suppressing the short channel effect thereby diminishes. Moreover, forming the pocket implant region 116 and the lightly doped region 114 hampers a further size reduction of the semiconductor device and an increase of the level of integration.